CY7C1565KV18-450BZXC Electronic Components

CY7C1565KV18-450BZXC Electronic Components belongs to 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency).All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

The CY7C1565KV18 is 1.8-V synchronous pipelined SRAM, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. 

The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

Product Features